* This file contains all the subcircuits to be used in SRAM256.cir

***** long channel VTP = -0.9, VTN = 0.8 *****
*.include modelcard/1um.pm
*.param supply = 5
*.param ll = 1u

****** 50nm models***


.include ./modelcard/50nm.pm
.param supply =1

.param lambda=25nm
.param ll='2*lambda'

****** 16nm low power models***
*.include ./modelcard/PTM_LP/16nm.pm
*.param supply =0.9
*.param ll=16nm

****** 16nm high peformance models***
*.include ./modelcard/PTM_HP/16nm.pm
*.param supply =0.7
*.param ll=16nm


* wire model
.subckt wire iot iof len=2112 wid=4
.param rr=0.3
.param cc='100e-15'
rt iot iof 'rr*len*50/(wid)'
cf iof  0  'cc*len*wid*50/1e6'
.ends wire

.subckt wire_dual lt rt lf rf len=10 wid=10
Xt lt rt wire len='len' wid='wid'
Xf lf rf wire len='len' wid='wid'
.ends wire_dual


* transistors and logic gates
.subckt nn d g s  ww=100
mnfet d g s 0 nmos L=ll w='ww*ll'
.ends

.subckt pp d g s   ww=100
mpfet d g s vdd pmos L=ll w='ww*ll'
.ends

.subckt inv out inn size=30 beta=2
XPP out inn vdd pp ww='size*beta/(beta+1)'
XNN out inn 0   nn ww='size/(beta+1)'
.ends inv

.subckt nnd2 out in1 in0 size=30 beta=2
Xap0 out in0 vdd pp ww='beta*size/(beta+2)'
Xap1 out in1 vdd pp ww='beta*size/(beta+2)'
Xan0 out in0 nng nn ww='2*size/(beta+2)'
Xan1 nng in1 0	 nn ww='2*size/(beta+2)'
.end nnd2

.subckt nor2 out in1 in0 size=30 beta=2
Xap0 ppi in0 vdd pp ww='2*beta*size/(2*beta+1)'
Xap1 out in1 ppi pp ww='2*beta*size/(2*beta+1)'
Xan0 out in0 0	 nn	ww='1*size/(2*beta+1)'
Xan1 out in1 0	 nn	ww='1*size/(2*beta+1)'
.ends nor2

.subckt nnd3 out in2 in1 in0 size=20 beta=2
Xp0 out in0 vdd pp ww='beta*size/(beta+3)'
Xp1 out in1 vdd pp ww='beta*size/(beta+3)'
Xp2 out in2 vdd pp ww='beta*size/(beta+3)'
Xn0 out in0 nn0 nn ww='3*size/(beta+3)'
Xn1 nn0 in1 nn1 nn ww='3*size/(beta+3)'
Xn2 nn1 in2 gnd nn ww='3*size/(beta+3)'
.ends


* latch, flipflop and reg
.subckt latch out inn clk clb size=15 beta=2
Xn inn clk qin nn ww='5'
Xp inn clb qin pp ww='10'
Xfp qin ggg vdd pp ww='5'
Xfn qin ggg gnd nn ww='5'
Xi ggg qin     inv size='size'
Xo out ggg     inv size='3*size'
.ends latch

.subckt flop qqq ddd clk
Xinve clb clk inv
Xflip int ddd clb clk latch
Xflop qqq int clk clb latch
.ends flop

.subckt reg8 ot7 ot6 ot5 ot4 ot3 ot2 ot1 ot0 in7 in6 in5 in4 in3 in2 in1 in0 clk
x7 ot7 in7 clk flop
x6 ot6 in6 clk flop
x5 ot5 in5 clk flop
x4 ot4 in4 clk flop
x3 ot3 in3 clk flop
x2 ot2 in2 clk flop
x1 ot1 in1 clk flop
x0 ot0 in0 clk flop
.ends reg8


*generates different data stream on all eight channels, buffered output
.subckt dat1 out period=1ns start=1ns sz=50 total=5 duty=3
*V0 j0  0  PULSE(0 'supply' 'start' 10p 10p 'duty*per-10ps' 'totalPer*per')
V0 j0  0  PULSE('supply' '0' 'start' 10p 10p 'duty*period' 'total*period')
x7 out j0 inv size='sz'
.ends dat1

.subckt dat8 o7 o6 o5 o4 o3 o2 o1 o0 per=1ns start=1ns size=50
V0 j0  0  PULSE(0 'supply' 'start' 10p 10p '0.5*per-10ps' 'per')
V1 j1  0  PULSE(0 'supply' 'start' 10p 10p '0.5*per-10ps' '2*per')
V2 j2  0  PULSE(0 'supply' 'start' 10p 10p '0.5*per-10ps' '3*per')
V3 j3  0  PULSE(0 'supply' 'start' 10p 10p '0.5*per-10ps' '4*per')
V4 j4  0  PULSE('supply' 0 'start' 10p 10p '0.5*per-10ps' '1*per')
V5 j5  0  PULSE('supply' 0 'start' 10p 10p '1*per-10ps' '2*per')
V6 j6  0  PULSE('supply' 0 'start' 10p 10p '1.5*per-10ps' '3*per')
V7 j7  0  PULSE('supply' 0 'start' 10p 10p '2*per-10ps' '4*per')
xb o7 o6 o5 o4 o3 o2 o1 o0 j7 j6 j5 j4 j3 j2 j1 j0 buf8 sz='size'
.ends dat8

.subckt buf8 ot7 ot6 ot5 ot4 ot3 ot2 ot1 ot0 in7 in6 in5 in4 in3 in2 in1 in0 sz=100
x7 ot7 in7 inv size='sz'
x6 ot6 in6 inv size='sz'
x5 ot5 in5 inv size='sz'
x4 ot4 in4 inv size='sz'
x3 ot3 in3 inv size='sz'
x2 ot2 in2 inv size='sz'
x1 ot1 in1 inv size='sz'
x0 ot0 in0 inv size='sz'
.ends buf8


* sense amplifier
.subckt senseAmp ot1 ot0 in1 in0 eva size=40
Xn0 ot0 in0 ot1 eva nnd3 size ='size'
Xn1 ot1 in1 ot0 eva nnd3 size ='size'
.ends senseAmp


* student defined models
.subckt decModel cho din clk sz=100
Xi1 nn1 din		inv	 size='sz'
Xn2 nn2 nn1 vdd nnd2 size='sz*1.9'
Xd2 dd1 nn1 gnd nnd2 size='sz*1.9'
Xn3 nn3 nn2 gnd nor2 size='sz*1.4'
Xd3 dd2 nn2 vdd nor2 size='sz*1.4*3'
Xn4 nn4 nn3 vdd nnd2 size='sz*0.32'
Xd4 rdw nn3 gnd nnd2 size='sz*0.32*15'
Xi5 nn5 nn4		inv
xn5 cho nn5 clk nnd2
.ends decModel


.subckt mem1 it if ac wid=10 len=10
xpst it ac tt  nn ww=5
xpsf if ac ff  nn ww=5
Xpif tt ff vdd pp ww=5
xpit ff tt vdd pp ww=5
Xnit tt ff gnd nn ww=5
xnif ff tt gnd nn ww=5
.ends mem1


.subckt write1 btt bff dii rwt clk sz=100 beta=2
x0	nrr	clk	inv size='sz/10'
x1	ng1 dii	inv	size='sz/10'
Xr0 ng0	nrr	rwt	nor2	size='sz/2'
Xn0	nnn	ng0	gnd nn	ww='2*sz/(beta+2)'
Xn1	btt	dii	nnn nn	ww='2*sz/(beta+2)'
Xn2	bff	ng1	nnn nn	ww='2*sz/(beta+2)'
Xp0 btt ng0 vdd pp	ww='beta*sz/(beta+2)'
Xp1 bff ng0 vdd pp	ww='beta*sz/(beta+2)'
.ends write1


.subckt read1 btt bff out rwt clk
Xnn ttt clk rwt nnd2 size=10
Xt1 tri ttt 	inv  size=20
Xsa tru	fal btt bff tri senseAmp size=50
Xit otr tru		inv	 size=20
Xif	fff fal		inv  size=20
Xii sff fff		inv  size=20
Xpu dot sff vdd pp ww=20
Xpd dot otr gnd nn ww=10
Xdf out dot inv
Xfb dot out inv size=10
.ends read1


.subckt readSub btt bff set rst rdw clk add
Xn1 nnn clk rdw add nnd3
Xi1	nni nnn			inv
Xsa set rst btt bff nni senseAmp size=50
.ends readSub


* 8 way readcollect
.subckt readcollect dot st7 rs7 st6 rs6 st5 rs5 st4 rs4 st3 rs3 st2 rs2 st1 rs1 st0 rs0
Xnd1 nn1 st7 st6 nnd2 size=10
Xnd2 nn2 st5 st4 nnd2 size=10
Xnd3 nn3 st3 st2 nnd2 size=10
Xnd4 nn4 st1 st0 nnd2 size=10
Xnd5 ng1 rs7 rs6 nnd2 size=10
Xnd6 ng2 rs5 rs4 nnd2 size=10
Xnd7 ng3 rs3 rs2 nnd2 size=10
Xnd8 ng4 rs1 rs0 nnd2 size=10
Xi1  pg1 nn1	 inv  size=20
Xi2  pg2 nn2	 inv  size=20
Xi3  pg3 nn3	 inv  size=20
Xi4  pg4 nn4	 inv  size=20
Xt1  dot pg1 vdd pp	  ww=20
Xt2  dot pg2 vdd pp	  ww=20
Xt3  dot pg3 vdd pp	  ww=20
Xt4  dot pg4 vdd pp	  ww=20
Xt5  dot ng1 gnd nn	  ww=10
Xt6  dot ng2 gnd nn	  ww=10
Xt7  dot ng3 gnd nn	  ww=10
Xt8  dot ng4 gnd nn	  ww=10
Xi5  doi dot	 inv  size=20
Xi6  dot doi	 inv  size=20
.ends readcollect