*Kiernan Canavan's SRAM_bits
* This file contains all the subcircuits to be used in SRAM256.cir

***** long channel VTP = -0.9, VTN = 0.8 *****
*.include modelcard/1um.pm
*.param supply = 5
*.param ll = 1u

****** 50nm models***


.include ./50nm.pm
.param supply =1

.param lambda=25nm
.param ll='2*lambda'

****** 16nm low power models***
*.include ./16nm.pm
*.param supply =0.9
*.param ll=16nm

****** 16nm high peformance models***
*.include ./16nm.pm
*.param supply =0.7
*.param ll=16nm


*.subckt wire iot iof len=10 wid=10
*.param rr=0.8
*.param cc = '200e-15'
*rt iot iof 'rr*len*50/(wid)'
*cf iof  0  'cc*len*wid*50/1e6'
*
*.ends

.subckt wire iot iof len=10 wid=10
.param rr=0.4
.param cc = '100e-15'
rt iot iof 'rr*len*50/(wid)'
cf iof 0 'cc*len*wid*50/1e6'
.ends

*For our 4 column model len=3168 and wid=25
.subckt wire_dual lt rt lf rf len=3168 wid=25
Xt lt rt wire len='len' wid='wid'
Xf lf rf wire len='len' wid='wid'
.ends

.subckt nn d g s  ww=100
mnfet d g s 0 nmos L=ll w='ww*ll'
.ends

.subckt pp d g s   ww=100
mpfet d g s vdd pmos L=ll w='ww*ll'
.ends


.subckt inv out inn size=30 beta=2
XPP out inn vdd pp ww='size*beta/(beta+1)'
XNN out inn gnd nn ww='size/(beta+1)'
.ends

.subckt nnd2 out in1 in0 size=30 beta=2
Xap0 out in0 vdd pp ww='beta*size/(beta+2)'
Xap1 out in1 vdd pp ww='beta*size/(beta+2)'
Xan0 out in0 nng nn ww='2*size/(beta+2)'
Xan1 nng in1 0   nn ww='2*size/(beta+2)'
.ends nnd2

.subckt nor2 out in1 in0 size=30 beta=2
Xap0 ppi in0 vdd pp ww='2*beta*size/(2*beta+1)'
Xap1 out in1 ppi pp ww='2*beta*size/(2*beta+1)'
Xan0 out in0 0 nn ww='1*size/(2*beta+1)'
Xan1 out in1 0   nn ww='1*size/(2*beta+1)'
.ends nor2

.subckt latch out inn clk clb size=15 beta=2
Xn inn clk qin nn ww='5'
Xp inn clb qin pp ww='10'

Xfp qin ggg vdd pp ww='5'
Xfn qin ggg gnd nn ww='5'

Xi ggg qin     inv size='size'
Xo out ggg     inv size='3*size'
.ends latch

.subckt flop qqq ddd clk
Xinve clb clk inv
Xflip int ddd clb clk latch
Xflop qqq int clk clb latch
.ends flop

.subckt reg8 ot7 ot6 ot5 ot4 ot3 ot2 ot1 ot0 in7 in6 in5 in4 in3 in2 in1 in0 clk
x7 ot7 in7 clk flop
x6 ot6 in6 clk flop
x5 ot5 in5 clk flop
x4 ot4 in4 clk flop
x3 ot3 in3 clk flop
x2 ot2 in2 clk flop
x1 ot1 in1 clk flop
x0 ot0 in0 clk flop
.ends reg8

.subckt dat1 out period=1ns start=1ns sz=50 total=5 duty=3
V0 j0  0  PULSE('supply' 0 'start' 10p 10p 'duty*period-10ps' 'total*period')
x7 out j0 inv size='sz'
.ends dat1

*generates different data stream on all eight channels, buffered output
.subckt dat8 o7 o6 o5 o4 o3 o2 o1 o0 per=1ns start=1ns size=50
V0 j0  0  PULSE(0 'supply' 'start' 10p 10p '0.5*per-10ps' 'per')
V1 j1  0  PULSE(0 'supply' 'start' 10p 10p '0.5*per-10ps' '2*per')
V2 j2  0  PULSE(0 'supply' 'start' 10p 10p '0.5*per-10ps' '3*per')
V3 j3  0  PULSE(0 'supply' 'start' 10p 10p '0.5*per-10ps' '4*per')
V4 j4  0  PULSE('supply' 0 'start' 10p 10p '0.5*per-10ps' '1*per')
V5 j5  0  PULSE('supply' 0 'start' 10p 10p '1*per-10ps' '2*per')
V6 j6  0  PULSE('supply' 0 'start' 10p 10p '1.5*per-10ps' '3*per')
V7 j7  0  PULSE('supply' 0 'start' 10p 10p '2*per-10ps' '4*per')
xb o7 o6 o5 o4 o3 o2 o1 o0 j7 j6 j5 j4 j3 j2 j1 j0 buf8 sz='size'
.ends dat8

.subckt buf8 ot7 ot6 ot5 ot4 ot3 ot2 ot1 ot0 in7 in6 in5 in4 in3 in2 in1 in0 sz=100
x7 ot7 in7 inv size='sz'
x6 ot6 in6 inv size='sz'
x5 ot5 in5 inv size='sz'
x4 ot4 in4 inv size='sz'
x3 ot3 in3 inv size='sz'
x2 ot2 in2 inv size='sz'
x1 ot1 in1 inv size='sz'
x0 ot0 in0 inv size='sz'
.ends buf8


.subckt nnd3 out in2 in1 in0 size=20 beta=2
Xp0 out in0 vdd pp ww='beta*size/(beta+3)'
Xp1 out in1 vdd pp ww='beta*size/(beta+3)'
Xp2 out in2 vdd pp ww='beta*size/(beta+3)'
Xn0 out in0 nn0 nn ww='3*size/(beta+3)'
Xn1 nn0 in1 nn1 nn ww='3*size/(beta+3)'
Xn2 nn1 in2 gnd nn ww='3*size/(beta+3)'
.ends

.subckt senseAmp ot1 ot0 in1 in0 eva size=40
Xn0 ot0 in0 ot1 eva nnd3 size ='size'
Xn1 ot1 in1 ot0 eva nnd3 size ='size'
.ends senseAmp

*.subckt decodeModel cho din clk sz=15
*Xi1  nn1 din inv      size = 'sz'
*Xnd2 nn2 nn1 vdd nnd2 size='2*sz*1'
*Xdu2 dd1 nn1 gnd nnd2 size = '2*sz'
*Xnr3 nn3 nn2 gnd nor2 size = '5*sz'
*Xdu3 dd2 nn2 vdd nor2 size = '5*sz*3*1'
*Xnd4 nn4 nn3 vdd nnd2 size = '2*sz'
*Xdu4 rdw nn3 gnd nnd2 size = '30*sz*1'
*Xnd5 ccc nn4 clk nnd2 size = '2*sz'
*Xi5  cho ccc     inv  size = 'sz'
*.ends decodeModel

*modified decodeModel sans 1 INV
.subckt decodeModel cho din clk sz=15
Xi1  nn1 din inv      size = 'sz'
Xnd2 nn2 nn1 vdd nnd2 size='2*sz*1'
Xdu2 dd1 nn1 gnd nnd2 size = '2*sz'
Xnr3 nn3 nn2 gnd nor2 size = '5*sz'
Xdu3 dd2 nn2 vdd nor2 size = '5*sz*3*1'
Xnd4 nn4 nn3 vdd nnd2 size = '2*sz'
Xdu4 rdw nn3 gnd nnd2 size = '30*sz*1'
Xi2  nn5 nn4 inv      size = 'sz'
Xnd5 cho nn5 clk nnd2 size = '2*sz'
.ends decodeModel

*modified decodeModel with flop in
*.subckt decodeModel cho din clk sz=15
*Xfl  dfl din clk flop
*Xi1  nn1 din inv      size = 'sz'
*Xnd2 nn2 nn1 vdd nnd2 size='2*sz*1'
*Xdu2 dd1 nn1 gnd nnd2 size = '2*sz'
*Xnr3 nn3 nn2 gnd nor2 size = '5*sz'
*Xdu3 dd2 nn2 vdd nor2 size = '5*sz*3*1'
*Xnd4 nn4 nn3 vdd nnd2 size = '2*sz'
*Xdu4 rdw nn3 gnd nnd2 size = '30*sz*1'
*Xnd5 cho nn4 clk nnd2 size = '2*sz'
*.ends decodeModel

*.subckt write1 btt bff dii rwt clk
*Xi1  nn1 clk     inv  size = '10'
*Xnr1 nn2 nn1 rwt nor2 size = '50'
*Xnm1 nn3 nn2 gnd nn   ww = '50'
*Xnm2 btt dii nn3 nn   ww = '50'
*Xnm3 bff nn4 nn3 nn   ww = '50'
*Xpm1 vdd nn2 btt pp   ww = '100'
*Xpm2 vdd nn2 bff pp   ww = '100'
*Xi2  nn4 dii     inv  size = '30'
*.ends write1

*new write subcircuit redesigned to work for cells not just super far away
*.subckt write1 btt bff dii rwt clk
*Xi1  nn1 rwt     inv  size = '10'
*Xnd1 nn7 clk nn1 nnd2 size = '50'
*Xi2  nn2 nn7     inv  size = '10'
*Xnm1 nn3 nn2 gnd nn   ww = '50'
*Xnm2 btt dii nn3 nn   ww = '50'
*Xnm3 bff nn4 nn3 nn   ww = '50'
*Xi3  nn4 dii     inv  size = '30'
*Xpm1 vdd clk btt pp   ww = '50'
*Xpm2 vdd clk bff pp   ww = '50'
*.ends write1

*Experimental write subcircuit with NAND3 enable pin for setting up as specific to one column
.subckt write1 btt bff dii rwt clk ena
Xi1  nn1 rwt     inv  size = '10'
Xnd1 nn7 clk nn1 ena nnd3 size = '50'
Xi2  nn2 nn7     inv  size = '10'
Xnm1 nn3 nn2 gnd nn   ww = '50'
Xnm2 btt dii nn3 nn   ww = '50'
Xnm3 bff nn4 nn3 nn   ww = '50'
Xi3  nn4 dii     inv  size = '30'
Xpm1 vdd clk btt pp   ww = '50'
Xpm2 vdd clk bff pp   ww = '50'
.ends write1

*Write with NAND3 and flop din
*.subckt write1 btt bff dii rwt clk ena
*Xfl  dfl dii clk flop
*Xi1  nn1 rwt     inv  size = '10'
*Xnd1 nn7 clk nn1 ena nnd3 size = '50'
*Xi2  nn2 nn7     inv  size = '10'
*Xnm1 nn3 nn2 gnd nn   ww = '50'
*Xnm2 btt dfl nn3 nn   ww = '50'
*Xnm3 bff nn4 nn3 nn   ww = '50'
*Xi3  nn4 dfl     inv  size = '30'
*Xpm1 vdd clk btt pp   ww = '50'
*Xpm2 vdd clk bff pp   ww = '50'
*.ends write1

*.subckt read1 btt bff dot rwt clk
*Xnd1 nn1 rwt clk nnd2 size = '10'
*Xi1  nn2 nn1     inv  size = '20'
*Xsa0 nn3 nn4 bff btt nn2 senseAmp size = '50'
*Xi2  nn5 nn3     inv  size = '20'
*Xi3  nn6 nn5     inv  size = '20'
*Xi4  nn7 nn4     inv  size = '20'
*Xpm1 nn8 nn6 vdd pp   ww = '20'
*Xnm1 gnd nn7 nn8 nn   ww = '10'
*Xi5  nn8 dot     inv  size = '20'
*Xi6  dot nn8     inv  size = '10'
*.ends read1

*read with clocked Dout
*.subckt read1 btt bff dot rwt clk
*Xnd1 nn1 rwt clk nnd2 size = '10'
*Xi1  nn2 nn1     inv  size = '20'
*Xsa0 nn3 nn4 bff btt nn2 senseAmp size = '40'
*Xi2  nn5 nn3     inv  size = '20'
*Xi3  nn6 nn5     inv  size = '20'
*Xi4  nn7 nn4     inv  size = '20'
*Xpm1 nn8 nn6 vdd pp   ww = '20'
*Xnm1 gnd nn7 nn8 nn   ww = '10'
*Xi5  nn8 flo     inv  size = '20'
*Xi6  flo nn8     inv  size = '10'
*Xfl  flo dot clk flop
*.ends read1


.subckt mem1 it if ac
Xpm1 nn1 nn2 vdd pp  ww=5
Xpm2 nn2 nn1 vdd pp  ww=5
Xnm1 it  ac  nn1 nn  ww=5
Xnm2 gnd nn2 nn1 nn  ww=5
Xnm3 gnd nn1 nn2 nn  ww=5
Xnm4 if  ac  nn2 nn  ww=5
.ends mem1

*.subckt readSub btt bff set rst rdw clk sz=100 beta=2
*Xnd1 nn1 rdw clk nnd2 size = 'sz'
*Xi1  trg nn1     inv  size = 'sz'
*Xsa1 rst set btt bff trg senseAmp size = '50'
*.ends readSub

*readSub with decoder model
.subckt readSub btt bff set rst rdw clk ena sz=100 beta=2
Xnd1 nn1 rdw clk ena nnd3 size = 'sz'
Xi1  dml nn1     inv  size = 'sz'
Xdm  trg dm1 clk decodeModel
Xsa1 rst set btt bff trg senseAmp size = '15'
.ends readSub

.subckt readcollect dot st3 rs3 st2 rs2 st1 rs1 st0 rs0 sz=30 beta=2
Xnd0 io0 rs1 rs0 nnd2 size = 'sz'
Xnd1 io1 rs3 rs2 nnd2 size = 'sz'
Xnd2 aa1 st1 st0 nnd2 size = 'sz'
Xnd3 aa0 st3 st2 nnd2 size = 'sz'
Xi0  hi0 aa0     inv  size = 'sz'
Xi1  hi1 aa1     inv  size = 'sz'
Xiy  dot nnn     inv  size = 'sz'
Xix  nnn dot     inv  size = 'sz'
Xpm0 dot hi0 vdd pp   ww = '20'
Xpm1 dot hi1 vdd pp   ww = '20'
Xnm0 gnd io1 dot nn   ww = '10'
Xnm1 gnd io0 dot nn   ww = '10'
.ends readcollect
*if issue check dot "node"