* File includes subcircuits and technology definitions
.include ./Kiernan'sSRAM_bits.cir


*this cell emulates load from SRAM cells,
* Number refers to the load from than number of cells
.subckt memLoad ttt fff number=254
Xnt ttt gnd dead nn ww='number*5'
Xnf fff gnd dead nn ww='number*5'
.ends memLoad

*Scott's SRAM64
.subckt fourBlock set rst adr din rdw clk
Xwr bt1 bf1 din rdw clk write1
.ends fourBlock

*********begin: topLevel*****

* Parameters
.global gnd vdd
.param gnd=0


*********begin: topLevel*****
.param per = 5ns
.param dataLead=500ps
.param lw=3168
.param wirew=25
*after measuring actual layout I obtain 3020 wire length
*Current Layour has 4 1x64 SRAM columns so length here is 1/4 total
*Good Bf1 and Bt1 pull-up at 30nS
*Passable Bf1 and Bt1 pull-up at 10nS
*Poor Bf1 and Bt1 pull-up at 5nS

vdd vdd 0 'supply'

Xclok clk               dat1 period='per' start='per+dataLead' total=1 duty=0.5 sz=50
Xrdwr rdw               dat1 period='per' start='2*per'        total=2 duty=1
Xdii din                dat1 period='per' start='per'          total=4 duty=2   sz=30
Xbit  ad0               dat1 period='per' start='0.5*per' total=3 duty=1
Xde   ope ad0 clk decodeModel size=20

*had as bt4 and bf4
Xwr bt1 bf1 din rdw clk vdd write1

Xw1 bt1 ct1 bf1 cf1     wire_dual len='lw' wid='wirew'
Xw2 bt2 ct2 bf2 cf2     wire_dual len='lw' wid='wirew'
Xw3 bt4 ct3 bf3 cf3     wire_dual len='lw' wid='wirew'
Xw4 bt4 ct4 bf4 cf4     wire_dual len='lw' wid='wirew'
Xmd1 bt1 bf1             memLoad number =63
Xmd2 bt2 bf2             memLoad number =64
Xmd3 bt3 bf3             memLoad number =64
Xmd4 bt4 bf4             memLoad number =64
Xwt1 bt1 bt2 wire
Xwt2 bt2 bt3 wire
Xwt3 bt3 bt4 wire
Xwf1 bf1 bf2 wire
Xwf2 bf2 bf3 wire
Xwf3 bf3 bf4 wire

Xla bt1 bf1 ope         mem1

Xrd bt1 bf1 set rst rdw clk vdd readSub


Xrc dot set rst vdd vdd vdd vdd vdd vdd readcollect


.ic V(la:nn2)=0 V(la:nn1)=1
.ic V(bt2)=1
.tran 1p 'per*10'