Our team developed the Pulse Delay Generator (PDG), an open-source, FPGA-based system intended for hardware security robustness testing through precise voltage glitching for fault injection attacks. The PDG employs a unique asynchronous Time-to-Digital Converter (TDC) and delay element architecture designed within the FPGA fabric, enabling highly accurate, sub-nanosecond pulse delays while compensating for asynchronous triggers to significantly reduce jitter. Additionally, a custom high-speed PCB ensures optimal signal integrity, while our tailored communication protocol seamlessly connects a Python-based GUI to the FPGA via USB, enabling intuitive user interaction, including arming, resetting, and configuring system parameters with minimal effort. Our most notable achievement is the implementation of an optional external clock input, a unique feature unmatched by commercial alternatives, that enables further jitter reduction when paired with a high-quality clock source. Achieving reliable synchronization with an external clock proved challenging, requiring careful attention to physical routing and clock-domain synchronization. Separately, ensuring precise sub-cycle delays necessitated meticulous manual wiring and hand-placement of FPGA primitives, along with exact tuning of the Vernier delay lines and TDC architecture.