This project focuses on developing next-generation gate driver circuits for thin-film transistor (TFT) displays using all-n-type oxide TFT technology made from a novel amorphous silicon material. The work combines research, circuit design, and simulation to investigate how our novel transistors can improve display performance while reducing power consumption, manufacturing complexity, and device sizing. The project investigates modern gate-on-array (GOA) architectures, reviewing signal timing, pulse control, and methods for improving reliability in high-resolution and high refresh rate displays. Using SPICE simulation tools and device models provided by our partner Amorphyx, multiple circuit designs are modeled and tested to evaluate factors such as voltage behavior, timing accuracy, power efficiency, and resistance to electrical noise or device variation. The goal is to compare these new and improved designs against other GOA approaches from research and identify improvements in efficiency, integration, and overall display reliability. This project supports ongoing industry trends toward thinner, lower-cost, and more flexible display technologies. This project was conducted in partnership with Amorphyx, as a part of ongoing research into next-generation display technology.