256 bit SRAM Layout and Simulation (ECE 471)

By

Kiernan Canavan

As part of my VLSI design class we laid out an SRAM cell and arrayed it into a 256 bit SRAM array. We next designed a read, write, and decode module and simulated their operation in LTSPICE with an RC wire model.

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Artifacts

Name Description
SRAM layout The included .jelib contains the Electric VLSI EDA tool layout of my my single SRAM cell as well as a 2x2 array.   Download
LTSPICE Component Netlists This LTSPICe file contains the subcircuit netlists of my SRAM, decoder, write block, read block, and wire model. Many of the subcircuit declarations and the file layout itself were created by my professor Dr. Scott Fairbanks.   Download
SRAM Test File This LTSPICE file was created by Dr. Scott Fairbanks to test the overall operation of our subcircuits and wire model by continually writing and reading one cell. I modified it to account for the 4 column 1x64 SRAM layout I believed to operate most effectively with my wire lengths and layout.   Download
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